Spec Update

Removed Indirection Register.
Added new location type to replace use of indirection register.
Added logic instrictions NOT/AND/OR/XOR/SHL/SHR/BTS/BTC.
Increased port count to 255.

SPEC.txt

@@ -1,28 +1,27 @@
 Features
-	- 1 16-bit Indirection register
 	- 4 16-bit Registers
 	- 255 8-bit Flag Registers
-	- 8 8-bit Ports
+	- 255 8-bit Ports
 		- 0 console in/out
 		- 1 tape in/out
+		- 2-32 Reserved
+		- Others Implementation Specific
 	- Program Counter
-	- Call Stack 16 x 8-bit
+	- Call Stack 16 x 16-bit
-	- 65535 x 8-bit Memory
+	- 64K x 8-bit Memory
 	- MSB / big-endian
 
-Registers (R)
+Registers (R)	A-D -> 0-3
-	A-D -> 0-3
+Marker (:)		:XYZ
-
-Markers (:)
-	:NAME
 
 Locations (@)
-Code	ASM		Type			Values
+Code	ASM		Type				Values
-0x0		P		Port			#
+0x0		P		Port				0-255
-0x1		R		Register		A-D
+0x1		R		Register			A-D
-0x2		M		Memory			0-65535
+0x2		M		Memory				0-65535
-0x3		L		Literal			0-65535 | 'a' | "a" | 0xFFFF
+0x3		I		Immediate			0-65535 | 'a' | "a" | 0xFFFF
-0x4		F		Flag			0-255
+0x4		F		Flag				0-255
+0x5		A		Address In Register	A-D
 
 Instructions
 
@@ -36,13 +35,6 @@ Code	ASM
 0x13	LOADL	R	@
 0x14	SAVEH	R	@
 0x15	SAVEL	R	@
-	Indirection
-0x60	LOADI	R
-0x61	SAVEI	R
-0x62	CLRI
-0x63	INCI
-0x64	DECI
-0x65	SETI	R
 	Accumulator
 0x20	CLR		R
 0x21	ADD		R	@
@@ -51,11 +43,19 @@ Code	ASM
 0x24	MUL		R	@
 0x25	INC		R
 0x26	DEC		R
+	Logic
+0x30	NOT		R
+0x31	AND		R	@
+0x32	OR		R	@
+0x33	XOR		R	@
+0x33	SHL		R	0-8		Shift Left
+0x34	SHR		R	0-8		Shift Right
+0x35	BTS		R	0-8		Bit Set
+0x36	BTC		R	0-8		Bit Clear
 	Stack
-0x40	CALL	#
+0x40	CALL	#|:
 0x41	RET
 	Program Flow
-		:Marker
 0x50	HALT
 0x51	JMP		#|:
 0x52	JZ		R #|: