Updated filenames
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199
arduino/Memory.cpp
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199
arduino/Memory.cpp
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/*
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Copyright 2018 Sam Stevens
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "Memory.h"
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Memory::Memory(uint8_t csPin) {
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//Set cs pin high
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this->csPin = csPin;
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pinMode(csPin, OUTPUT);
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digitalWrite(csPin, HIGH);
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//Default to 64k ram
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this->memSize = 0xFFFF;
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//Store spi setting
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this->setting = SPISettings(20000000, MSBFIRST, SPI_MODE0);
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}
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void Memory::start() {
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digitalWrite(this->csPin, LOW);
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SPI.beginTransaction(this->setting);
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}
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void Memory::end() {
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SPI.endTransaction();
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digitalWrite(this->csPin, HIGH);
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}
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bool Memory::init() {
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//Set mode to sequential access (should be default mode)
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this->start();
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SPI.transfer(INSTR_WRMR);
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SPI.transfer(MODE_SEQ);
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this->end();
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//Verify that it was set
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this->start();
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SPI.transfer(INSTR_RDMR);
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uint8_t mode = SPI.transfer(0);
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this->end();
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return mode == MODE_SEQ;
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}
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uint16_t Memory::getSize() {
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return this->memSize;
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}
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void Memory::setSize(uint16_t memSize) {
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this->memSize = memSize;
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}
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uint8_t Memory::read(uint16_t addr) {
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this->start();
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SPI.transfer(INSTR_READ);
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SPI.transfer16(addr);
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uint8_t data = SPI.transfer(0);
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this->end();
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return data;
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}
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void Memory::write(uint16_t addr, uint8_t data) {
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this->start();
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SPI.transfer(INSTR_WRITE);
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SPI.transfer16(addr);
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SPI.transfer(data);
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this->end();
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}
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void Memory::writeRange(uint8_t data, uint16_t from, uint16_t to) {
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if (from > to) {
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return;
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}
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this->start();
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SPI.transfer(INSTR_WRITE);
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SPI.transfer16(from);
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for(uint32_t i = from; i < to; i++) {
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SPI.transfer(data);
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}
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this->end();
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}
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bool Memory::verifyRange(uint8_t data, uint16_t from, uint16_t to) {
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if (from > to) {
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return false;
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}
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this->start();
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SPI.transfer(INSTR_READ);
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SPI.transfer16(from);
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bool ok = true;
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for(uint32_t i = from; i < to; i++) {
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if (SPI.transfer(0) != data) {
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ok = false;
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break;
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}
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}
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this->end();
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return ok;
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}
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bool Memory::test() {
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//write 0x55 (01010101)
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this->writeRange(0x55, 0, this->memSize);
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//verify
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if (!this->verifyRange(0x55, 0, this->memSize)) {
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return false;
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}
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//write zeros
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this->writeRange(0, 0, this->memSize);
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//verify zeros
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if (!this->verifyRange(0, 0, this->memSize)) {
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return false;
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}
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return true;
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}
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uint8_t MemoryCache::getSize() {
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return this->cacheElements;
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}
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MemoryCacheItem* MemoryCache::getItem(uint8_t index) {
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if (index < this->cacheElements) {
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return &this->cache[index];
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}
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return NULL;
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}
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MemoryCache::MemoryCache(uint8_t cacheElements, Memory& memory) {
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this->memory = &memory;
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this->cache = (MemoryCacheItem*)calloc(cacheElements, sizeof(MemoryCacheItem));
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this->cacheElements = cacheElements;
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}
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uint8_t MemoryCache::read(uint16_t addr) {
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bool found = false;
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uint8_t data = 0;
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//Find in cache
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for(uint8_t i = 0; i < this->cacheElements; i++) {
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if (this->cache[i].valid) {
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if (this->cache[i].addr == addr) {
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if (this->cache[i].ttl < UINT8_MAX - 1) {
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this->cache[i].ttl = UINT8_MAX;
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}
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data = this->cache[i].data;
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found = true;
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}
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}
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}
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if (found) {
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return data;
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}
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//Not found, read from memory and add to cache
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data = this->memory->read(addr);
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//Decrement TTLs
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for(uint8_t i = 0; i < this->cacheElements; i++) {
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if (this->cache[i].ttl > 0) {
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this->cache[i].ttl--;
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}
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}
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uint8_t foundTTL = UINT8_MAX;
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uint8_t cacheSlot = 0;
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for(uint8_t i = 0; i < this->cacheElements; i++) {
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if (!this->cache[i].valid) {
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cacheSlot = i;
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break;
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}
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if (this->cache[i].ttl < foundTTL) {
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cacheSlot = i;
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}
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}
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this->cache[cacheSlot].addr = addr;
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this->cache[cacheSlot].data = data;
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this->cache[cacheSlot].ttl = UINT8_MAX;
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this->cache[cacheSlot].valid = true;
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return data;
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}
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void MemoryCache::update(uint16_t addr, uint8_t data) {
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for(uint8_t i = 0; i < this->cacheElements; i++) {
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if (this->cache[i].valid && this->cache[i].addr == addr) {
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this->cache[i].data = data;
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break;
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}
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}
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}
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